decoding circuit造句
例句與造句
- The parallel form of the input sequence is decoded by means of a logical decoding circuit .
此并行形式序列通過邏輯解碼電路輸入。 - An application of logic devices able to program to the decoding circuit
可編程邏輯器件在譯碼電路中的應用 - Colour decoding circuit
彩色解碼電路 - The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3 . 2k internal fifo cache embedded , at the scale of 46k gates . its encoding and decoding speed are 66mhz and 47mhz respectively
布局布線后結果表明本文所設計的rs編碼器的速度可達到66mhz ；解碼速度可達到47mhz ，電路規模為4 . 6萬門，包含有3 . 2k的內部緩存fifo的rs編/解碼電路。 - The hardware system includes power supply circuit , clock reset circuit , jtag model building circuit , decoding circuit , memory interface circuit , man - machine interface circuit and numeric control constant - current source interface circuit
硬件系統主要包括電源電路、時鐘復位電路、 jtag仿真接口電路，譯碼電路、存儲器接口電路、人機接口電路、 adc轉換電路和數控恒流源接口等。 - It's difficult to find decoding circuit in a sentence. 用decoding circuit造句挺難的
- Chapter two addresses in details systematic design and related modules of stand - alone door - lock system . the modules include mcu , recognition module , power , lcd , guide voice , i / o decoding circuit , rtc , unlock circuit , power save and anti - interference design
第二部分著重介紹了指紋門禁單機系統的系統總體設計以及系統中涉及到的各模塊的基礎知識、設計思路和具體實現。 - In this paper we discuss mca circuit , the sequential logic for mca data collection , for the setting of the uld , lld and the gain of pga , as well as the combinational logic for decoding circuits of the computer interface , based on cpld
本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據采集的時序控制邏輯、閾值設定和程控放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機接口的譯碼電路等組合控制邏輯。 - The application of hardware decoding circuit is widely , because it not only can be used on computer , but also can be used on consumer equipment like digital - tv and dvd - player . the avs and h . 264 standards and the architecture of digital video decoder chip are investigated in the thesis , and a high - definition multi - mode decoder soc chip is proposed . the chip can support avs level 4 . 0 / 6 . 0 and h . 264 main profile level 4 . 0
本文在研究了avs和h . 264視頻編碼標準和數字視頻解碼芯片系統結構的基礎上,設計了同時支持avs和h . 264的高清解碼soc芯片,能夠對avslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。 - It emphatically describes address decoding circuit and controling circuit of fpga in hardware , and describes dma transmission mode and disposing of the interrupt in driver , and describes how to get data from wav file , and how to organize data before transmition , and how to chose appropriate quantity of data transmition every time in application
著重闡述了硬件設計中fpga內部重要的譯碼及控制電路設計,驅動程序中dma ( directmemoryaccess )的傳輸及中斷處理,應用程序中對于兩個聲音文件數據的正確獲取、組合及分割等問題。 - There are several aspects of work that was done in this thesis mainly . firstly , the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed . secondly , decoding circuit of the under - water long - range remote control system was designed with fpga , including vhdl coding , simulation , synthesis , place & route , etc . besides , power consumption to fpga that is designed is estimated in this thesis . lastly , we designed and made one pcb to verify and test fpga decoding chip that is designed , and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理并進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga芯片完成了水下遠程遙控fpga解碼芯片的設計工作，包括硬件描述語言( vhdl )編碼、電路前后仿真、綜合和布局布線工作，并對設計的fpga解碼芯片進行了初步的功耗估算；最后設計制作了一塊fpga解碼芯片電路驗證測試板，并完成了電路調試和測試。 - On the basis of analyzing the old system and theory , the element circuits of wireless digital audio transceiver modules are designed in detail including the digital audio encoding and decoding circuits with the surrounding circuits , the fsk circuit based on pll frequency synthesizer , the power amplifier circuit , the frequency discrimination and agc circuit
在分析原系統結構和理論的基礎上,完成了整個無線數字音頻傳輸模塊各單元電路的設計。主要包括有數字音頻編碼和解碼電路及外圍電路的設計、基于鎖相頻率合成器理論的fsk電路設計、功率放大器的設計、鑒頻與agc控制電路的設計。 - In the part , there are following contents : single - chip and memory circuit , interrupt control circuit , decoding circuit , parameter area circuit , watchdog circuit and serial communication interface circuit , etc . in this paper , serial communication interfaces between upper pc and lower single - chips are designed
其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串行通信接口電路設計等。